Pseudo random self-test architecture for Advanced Encryption Standard

Abstract

A pseudo random test strategy for the AES is presented in this paper, suitable for fault tolerant cryptographic designs. The proposed solution is capable of assessing the integrity of a crypto-chip in a non-concurrent, autonomous manner. The error detection strategy relies on iterated execution of the crypto-system's components in order to reduce the complexity of the test architecture and the test length. Alternative verification structures are considered with respect to uniform pseudo random stimulation of the datapath and the key scheduler. Furthermore, the proposed test method offers a good trade-off between the length of the test process and the storage requirements for the correct responses. The article investigates the integration of the proposed error detection technique into fault tolerant designs. The presented test architecture entails reduced area overhead.