Comparing CMOS And BICMOS NOR Decoder Structures Using A Monte Carlo Optimization Tool

Abstract

In this work the driveability of CMOS and BICMOS NOR decoders are investigated. An optimization procedure is used to find out the ideal dimension of the transistors in order to get maximum circuit speed. The BICMOS version shows higher speed even at low capacitive loads and its area consumption nearly remains constant even at high capacitive loads. For a load capacity of 3pF a maximal factor 2 of speed improvement for BICMOS is archieved covering the same area as the appropriate CMOS one. For high capacitive loads (50pF) the BICMOS speed improvement is reduced (factor 1.1), but there is still an advantage of area conservation (factor 7.5).