Hardware acceleration architecture for EtherCAT master controller

Abstract

EtherCAT is an Industrial Ethernet that is suitable where high-speed communication and highly accurate synchronization are required. An EtherCAT master is generally built using software and a common PC. However, building an EtherCAT master on an embedded microprocessor and on various operating systems makes it to implement the master software, develop applications, and achieve high-speed communication. We propose an EtherCAT accelerator that manipulates frames and cyclic executions in dedicated hardware for master processing. The aim with this accelerator is to minimize interventions. We evaluated a field-programmable gate array prototype with standard Linux and a Geode processor (500MHz). The maximum communication processing time of 64 Bframe was less than 50 μs.