Power optimization in pipeline analog-to-digital converters

Abstract

In this paper, the power analysis and optimization are presented to aid the design of the pipeline analog-to-digital converters (ADC's). The dependency of the power dissipation on the main specifications of the analog-to-digital converters including the signal-to-noise ratio (SNR), the sampling rate, the power supply voltage, the effective stage resolutions, and the scaling index of the sampling capacitors are discussed. The low-power design technique for the pipeline ADC is presented. By using the presented low-power design technique, the optimum values of all the stage capacitors, the effective stage resolutions and the compensation capacitors of the two-stage operational amplifiers are simultaneously optimized.