Optimal design of second generation current conveyors by the Artificial Bee Colony technique

Abstract

The field of metaheuristics based on swarm intelligence (SI) techniques, for the application to analog design optimization is a rapidly growing domain of research. This is due to the importance of these metaheuristics to solve NP-hard problem. The main goal of this paper is to use the Artificial Bees Colony (ABC) technique to the optimal sizing of analog circuits. The paper details the proposed algorithm and highlights its performances using some mathematical test functions. An application to the optimal sizing of CMOS second generation current conveyors (CCII) for specific performances is presented, and comparison results with published works are highlighted. SPICE simulation results are given to show the viability of the suggested algorithm.