Clock controller design in SuperSPARC II microprocessor

Abstract

This paper describes the SuperSPARC II clock controller. This controller allows the internal clock to be disabled during the chip's normal operation. Then any number of internal clock pulses can be issued in a controlled fashion. The clock can return to the free running mode after being disabled. All clock control is done in a way that produces no glitches on the internal clock signal The clock controller can be accessed through the IEEE 1149.1 interface, making it useful at the chip level and at the module or system level.