Frequency adaptivity improvement in GDSC-PLL

Y. N. Batista, H. Souza, F. Neves
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Abstract

This paper shows a scheme for improving the detection performance of the Fundamental-Frequency Positive-Sequence (FFPS) space vector through the Generalized Delayed Signal Cancellation Phase-Locked Loop (GDSC-PLL). The performance was improved by a new scheme that reduces the phase-angle error in the frequency adaptive scheme during grid frequency variations. In the new scheme we replaced the SRF-PLL used for the frequency adaptation scheme by simple samples counters. Further, we made improvements in the circuitry that performs the frequency estimation filtering. The performances of the traditional GDSC-PLL and other usual detection schemes were compared with the proposed one through transient test cases based on IEC 61000 and typical electrical events. The new approach led to a reduction of up to 79% in the phase-angle convergence time right after disturbances and a reduction of up to 65% in the mean absolute error during frequency variation.
GDSC-PLL频率自适应改进
提出了一种利用广义延迟信号抵消锁相环(GDSC-PLL)提高基频正序列(FFPS)空间矢量检测性能的方案。通过减小电网频率变化时频率自适应方案的相角误差,提高了系统的性能。在新方案中,我们用简单的采样计数器取代了用于频率自适应方案的SRF-PLL。此外,我们对执行频率估计滤波的电路进行了改进。通过基于iec61000的瞬态测试用例和典型电事件,比较了传统GDSC-PLL检测方案和其他常用检测方案的性能。新方法使干扰后的相角收敛时间减少了79%,频率变化期间的平均绝对误差减少了65%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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