A logistic regression yield model for SRAM bit fail patterns

Abstract

Yield models have been used in semiconductor manufacturing for quite some time with typically good success. Many of these yield models are used for determining the appropriate type and amount of redundancy in random access memories. The author describes the use of a yield model for SRAMs based on die level bit fail counts on a wafer through the use of a logistic regression model. The model uses a binary response for when a chip does or does not have bit failures recorded. Once a model is fit to the bit fail data, accurate yield loss estimates can be made of certain bit fail modes taking into account the amount of autocorrelation of bit fail categories on similar chips. This is necessary due to the high degree of bit fail clustering typically encountered in semiconductor manufacturing. Examples are given showing the actual versus the predicted model on a 128 kbit SRAM device. Discussion of the necessity of using a logistic model with a binary response as compared to other regression models using ordinary least squares (OLS) approaches. The benefits of this model are discussed with its assumptions and limitations. Typical applications of the model are also shown.