Guideline of Device Optimization for Ferroelectric InGaZnO Transistor

Abstract

The novel hafnium-zirconium oxide- (HZO-) based ferroelectric field-effect transistor with the InGaZnO channel (IGZO FeFET) has gained increasing interest due to its superior carrier mobility and low process temperature. However, the slow Erase speed is inevitable due to the intrinsic difficulty of IGZO channel inversion. Consequently, the floating of the channel region results in inefficient ferroelectric switching (FS) and an undesirable degradation of both operating speed and memory window. In this work, we provide a comprehensive device optimization guideline to mitigate the channel floating effect and enhance FS in the IGZO FeFET, including the deposition condition, thickness, and length of the IGZO channel.