{"title":"Critical thermal issues in nanoscale IC design","authors":"Lei Jiang, D. Pantuso, P. Sverdrup, W. Shih","doi":"10.1109/IRPS.2009.5173378","DOIUrl":null,"url":null,"abstract":"The array of thermal modeling tools demonstrated here provided a new methodology to improve design and reliability evaluations as we tackle the power-thermal issues with current IC design. Net-specific Tj and interconnect SH prediction, when applied on large megablock designs, lead to significant thermal margins and benefit for electromigration. The analysis here also highlighted challenges associated with device and interconnect scaling, especially the small-scale thermal interaction and power density increases. Global-local CAD approaches and research into nano-scale heat transfer are critical in making sure that future design can make efficient use of the silicon scaling that is afforded by Moore's law, as we enter the new era of scaling for energy-efficient processors [8].","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"265 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2009.5173378","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The array of thermal modeling tools demonstrated here provided a new methodology to improve design and reliability evaluations as we tackle the power-thermal issues with current IC design. Net-specific Tj and interconnect SH prediction, when applied on large megablock designs, lead to significant thermal margins and benefit for electromigration. The analysis here also highlighted challenges associated with device and interconnect scaling, especially the small-scale thermal interaction and power density increases. Global-local CAD approaches and research into nano-scale heat transfer are critical in making sure that future design can make efficient use of the silicon scaling that is afforded by Moore's law, as we enter the new era of scaling for energy-efficient processors [8].