Critical thermal issues in nanoscale IC design

Lei Jiang, D. Pantuso, P. Sverdrup, W. Shih
{"title":"Critical thermal issues in nanoscale IC design","authors":"Lei Jiang, D. Pantuso, P. Sverdrup, W. Shih","doi":"10.1109/IRPS.2009.5173378","DOIUrl":null,"url":null,"abstract":"The array of thermal modeling tools demonstrated here provided a new methodology to improve design and reliability evaluations as we tackle the power-thermal issues with current IC design. Net-specific Tj and interconnect SH prediction, when applied on large megablock designs, lead to significant thermal margins and benefit for electromigration. The analysis here also highlighted challenges associated with device and interconnect scaling, especially the small-scale thermal interaction and power density increases. Global-local CAD approaches and research into nano-scale heat transfer are critical in making sure that future design can make efficient use of the silicon scaling that is afforded by Moore's law, as we enter the new era of scaling for energy-efficient processors [8].","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"265 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2009.5173378","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

The array of thermal modeling tools demonstrated here provided a new methodology to improve design and reliability evaluations as we tackle the power-thermal issues with current IC design. Net-specific Tj and interconnect SH prediction, when applied on large megablock designs, lead to significant thermal margins and benefit for electromigration. The analysis here also highlighted challenges associated with device and interconnect scaling, especially the small-scale thermal interaction and power density increases. Global-local CAD approaches and research into nano-scale heat transfer are critical in making sure that future design can make efficient use of the silicon scaling that is afforded by Moore's law, as we enter the new era of scaling for energy-efficient processors [8].
纳米级集成电路设计中的关键热问题
本文展示的热建模工具阵列提供了一种新的方法来改进设计和可靠性评估,因为我们解决了当前IC设计中的功率-热问题。网络特定的Tj和互连SH预测,当应用于大型兆锁设计时,会带来显着的热裕度和电迁移的好处。这里的分析还强调了与器件和互连缩放相关的挑战,特别是小规模热相互作用和功率密度的增加。随着我们进入节能处理器的缩放新时代[8],全局局部CAD方法和纳米尺度传热研究对于确保未来设计能够有效利用摩尔定律提供的硅缩放至关重要。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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