A Hardware Architecture for Training of Artificial Neural Networks Using Particle Swarm Optimization

Abstract

Artificial Neural Networks (ANN) find applications in various fields of science and engineering. The training of ANN is an iterative process which consumes huge amount of time when executed on conventional microprocessors. It can be accelerated by adopting parallel computation techniques. This paper presents a Verilog HDL based parallel Hardware Architecture for ANN training using Particle Swarm Optimization (PSO) algorithm, which can be synthesized for a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC). PSO was preferred over a gradient descent method like Back Propagation (BP), because of its parallel nature and simplicity, which enables an easy hardware implementation. The proposed design was successfully simulated in ModelSim® and the simulation results were compared with those of a conventional MATLAB® code, wherein the former was found to be satisfactorily faster than the latter.