A practical interconnect driven ASIC design procedure

Abstract

To shorten design time, it is very important to correctly supply the wire load of nets to the synthesis tool before layout. In this paper, a procedure to create wire load models for a specific processing technology and design flow is presented. Also a physical to logical hierarchy mapping procedure is proposed such that the correct wire load model may be applied to drive synthesis before layout. We apply these methodologies to our company's products of 0.6 /spl mu/m technology as illustrations.