Realization of a systematic bit-wise decomposition metric

Chia-Wei Chang, Po-Ning Chen, Y.S. Han
{"title":"Realization of a systematic bit-wise decomposition metric","authors":"Chia-Wei Chang, Po-Ning Chen, Y.S. Han","doi":"10.1109/APCCAS.2004.1413067","DOIUrl":null,"url":null,"abstract":"In this paper, a realization structure for our previously proposed systematic recursive formula for bitwise decomposition of M-ary symbol metric is proposed, which can be applied to reduce the memory space and processing latency of a system where the information sequence is binary-coded and interleaved before M-ary modulated. Different from conventional structure where de-interleaver and decoder are separate circuits, our structure de-interleaves and decodes at the same time.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2004.1413067","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

In this paper, a realization structure for our previously proposed systematic recursive formula for bitwise decomposition of M-ary symbol metric is proposed, which can be applied to reduce the memory space and processing latency of a system where the information sequence is binary-coded and interleaved before M-ary modulated. Different from conventional structure where de-interleaver and decoder are separate circuits, our structure de-interleaves and decodes at the same time.
一个系统的逐位分解度量的实现
本文提出了一种系统递推矩阵的实现结构,该结构可用于减少信息序列在M-ary调制前二进制编码和交错的系统的存储空间和处理延迟。与传统的去交织器和解码器是独立电路的结构不同,我们的结构是同时进行去交织和解码的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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