Design and Implementation of High Speed, Low Area Multiported Loadless 4T Memory Cell

Abstract

In several applications, the embedded SRAMs can occupy the majority of the chip area and contain hundreds of millions of transistors. Since RAMs are critical to processor performance, researchers have sought to optimize their performance and efficiency through reconfiguration [1]. This paper presents the architecture and circuit design for a multiported SRAM building block. In this paper SRAM cell with load (6T) and without load (4T) is designed and implemented in 180nm technology and comparison between them was made in terms of power consumed, area used and access time. It was found that load less 4T SRAM cell consumes less power as compared to 6T SRAM cell and occupies lesser area. Here as an application example, 8X1 memory using load less 4T is implemented. The decoding here is again done with Traditional CMOS decoder and Lyon Schediwy decoder. It is observed that the later performs much better in terms of power, timing and is area efficient. The 6T and 4T load less memory cell is further converted for multiport operation and simulated for various performance parameters such as area, power and delay and compared.