At-speed built-in test for logic circuits with multiple clocks

Abstract

This paper presents an at-speed built-in test method for logic circuits with multiple clocks. It is clear that BIST (built-in self-test) plays a key role in test strategy for SoCs. It is also obvious that at-speed BIST is necessary for high quality test. Though several approaches enable at-speed BIST, there still exist several issues, such as multiple clocks, multi-cycle transfers and false paths. The proposed method realizes at-speed test for arbitrary combination of release and capture clocks at reasonable test time by utilizing the LFSR reseeding technique. Experimental results for benchmark circuits and an industrial circuit are given to illustrate the effectiveness of our approach.