{"title":"Reduction of fault detection costs through a BDD formalism","authors":"Fabrizio Ferrandi","doi":"10.1016/0165-6074(94)90052-3","DOIUrl":null,"url":null,"abstract":"<div><p>The paper presents a methodology for an efficient testability analysis of complex VLSI circuit. It is based on controllability/observability evaluation using Binary Decision Diagrams (BDD). Efficiency is improved by intelligent use of intermediate results.</p></div>","PeriodicalId":100927,"journal":{"name":"Microprocessing and Microprogramming","volume":"40 10","pages":"Pages 841-844"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0165-6074(94)90052-3","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microprocessing and Microprogramming","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/0165607494900523","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The paper presents a methodology for an efficient testability analysis of complex VLSI circuit. It is based on controllability/observability evaluation using Binary Decision Diagrams (BDD). Efficiency is improved by intelligent use of intermediate results.