Reduction of fault detection costs through a BDD formalism

Fabrizio Ferrandi
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引用次数: 1

Abstract

The paper presents a methodology for an efficient testability analysis of complex VLSI circuit. It is based on controllability/observability evaluation using Binary Decision Diagrams (BDD). Efficiency is improved by intelligent use of intermediate results.

通过BDD形式降低故障检测成本
本文提出了一种有效分析复杂VLSI电路可测试性的方法。它基于使用二进制决策图(BDD)的可控性/可观察性评估。通过智能地利用中间结果来提高效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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