Bridge-gap buried digit-line for high density stacked DRAMs

Abstract

Explores the interaction of design and process to achieve a manufacturable low digit-line resistance-a key element to DRAM (dynamic random access memory) speed and to minimizing overall process complexity. They propose an interaction between stacked DRAM design and process called the bridge-gap process for achieving low digit-line resistance while minimizing overall process complexity. A study of digit-line resistance as a function of word-line gap and digit-line poly-Si thickness indicates that there is a well-defined, poly-Si dependent forbidden gap which gives rise to high, variable, and even open digit-line resistance. After word-line (n-channel transistor) spacer formation, digit-line buried contact formation, and digit-line poly-Si deposition, this gap partially closes and so presents a deep trench, which the LPCVD (low pressure chemical vapor deposited) WSi/sub x/ cannot adequately cover. For a minimum digit-line poly-Si thickness that can withstand the WSi/sub x/ stress, word-line gaps are designed so that they are either less than (bridged digit-line) or greater than (gapped digit-line) the forbidden gap.<>