{"title":"PM effectiveness as a high leverage output improvement methodology","authors":"S. Saha, C. Kuppuswamy, J. Kraus","doi":"10.1109/ASMC.1995.484376","DOIUrl":null,"url":null,"abstract":"Intel Corporation has typically increased factory output by either adding more bottleneck equipment and/or improving equipment utilization. Utilization improvements were achieved by improving availability while maintaining the same or lower gap between availability and utilization. Typical availability improvement projects would require hardware changes (e.g. faster robots, faster pumps) or process changes, both of which have some level of technology risks. Lower risks from procedural changes make it an attractive alternate path for improvements. The seed idea for this program came from another Intel Fab experience which showed that right after a scheduled PM, the unscheduled downtimes would, immediately following a PM, almost double the baseline preceding the PM. This pointed to an opportunity to understand the PM content and its relationships to the equipment reliability since the experience indicated that, during every PM some \"damage\" was being done to the equipment which subsequently caused the post-PM failures. Since most of the improvements came from \"procedural\" improvements, this methodology has the added benefits of being \"low risk\". The \"Indy 500\" Team was formed in response to the low reliability of a tool that was factory output constraints. The Team consisted of all technicians from all shifts to improve teamwork, communication and training.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"9 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.1995.484376","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Intel Corporation has typically increased factory output by either adding more bottleneck equipment and/or improving equipment utilization. Utilization improvements were achieved by improving availability while maintaining the same or lower gap between availability and utilization. Typical availability improvement projects would require hardware changes (e.g. faster robots, faster pumps) or process changes, both of which have some level of technology risks. Lower risks from procedural changes make it an attractive alternate path for improvements. The seed idea for this program came from another Intel Fab experience which showed that right after a scheduled PM, the unscheduled downtimes would, immediately following a PM, almost double the baseline preceding the PM. This pointed to an opportunity to understand the PM content and its relationships to the equipment reliability since the experience indicated that, during every PM some "damage" was being done to the equipment which subsequently caused the post-PM failures. Since most of the improvements came from "procedural" improvements, this methodology has the added benefits of being "low risk". The "Indy 500" Team was formed in response to the low reliability of a tool that was factory output constraints. The Team consisted of all technicians from all shifts to improve teamwork, communication and training.