Instruction Set Design for a Nibble-Serial Signal Processing Element

Abstract

Programmable nibble-serial processors are an efficient means of implementation for signal processing algorithms involving the solution of difference equations. The architecture is based on a simple processing element, known as a Signal Processing Element (SPE), of which many could be fabricated on a single VLSI chip. This paper discusses the design of an instruction set for such an SPE, considering in particular the effects of data memory size, and the use of special purpose registers.