Design of CMOS Low Noise Amplifier for 5G Applications Using 45nm Technology

Abstract

In this paper, the comparison design of a two-stage Bulk CMOS (NMOS) low noise amplifier is implemented using 45 nm technology. These designed amplifiers can operate at a frequency range of 24–30 GHz. The amplifier is implemented using two stage Cascode configuration and shunt series peaking. A comparative study of designed Cascode configuration with feedforward technique, current bleeding technique, and differential configuration. The operation of the circuits in the millimeter-wave frequency band and is compared for gain, noise, power consumption and linearity. The different architectures were implemented for high performance with a power supply of 1.1V. The design is implemented by using two NMOS transistors on both stages, producing maximum transconductance with a minimum transistor width, which in turn makes the circuit operate faster. The use of the feed-forward technique implemented has helped to reduce noise and power consumption. The circuits were stimulated in the Keysight Agilent Design System software package using a 45nm Predictive technology model (PTM).