Yield modeling in a custom IC manufacturing line

Abstract

A methodology used to implement yield modeling in a custom integrated-circuit manufacturing facility is described. The sources for the inputs to the models are described. The component approach to yield modeling is explained, where component defect density (D/sub 0/) information is used to build an overall yield prediction. A reverse model using a single D/sub 0/ number is detailed. Verifications and selection criteria are given for model selection.<>