Impact of nanometer transistor on analog performance

Abstract

There is a serious concern on the time to market the product as transistor size continues to shrink. This is especially true in analog IC design where the impact on new process would require deep understanding of its parameters on design specifications. The nature of analog specifications which oppose each other adds more complexity in the fine tune design process. This paper explores this issue, concentrating on the impact of transistor size scaling on analog design in CMOS technology. Circuit performance - voltage gain, power dissipation, output voltage swing and cut-off frequency are observed throughout this paper to analyze the impact of transistor size scaling. Predictive transistor model (PTM) is used in this project for technology process of 130 nm, 90 nm, 65 nm, 45 nm and 32 nm.