{"title":"Direct state transfer in MLC based memristive ReRAM devices for ternary computing","authors":"D. Fey, J. Reuben","doi":"10.1109/ECCTD49232.2020.9218323","DOIUrl":null,"url":null,"abstract":"In this paper we present a new procedure for a direct state transfer in ReRAM based multi-level cell (MLC) memristors for future ternary data processing, i.e. the direct transitioning of one ternary MLC state to another state. According to the rules of a ternary stored-transfer-adder cell the content of two memristors storing three different resistance values are read out and processed by a sense amplifier to produce a new ternary state for two output memristors. In contrast to own older work the analogue-digital-converting of ternary MLC based memristors with subsequent digital processing is avoided what requires a comparatively high energy budget. The solution is based on an adapted version of an existing sense amplifier circuit realising an in-memory processing for a majority logic developed by our own. We present the new concept and simulation results characterising the functionality for the new memristive ternary MLC for a ReRAM technology from Innovations for High Performance Microelectronics (IHP).","PeriodicalId":336302,"journal":{"name":"2020 European Conference on Circuit Theory and Design (ECCTD)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 European Conference on Circuit Theory and Design (ECCTD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD49232.2020.9218323","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this paper we present a new procedure for a direct state transfer in ReRAM based multi-level cell (MLC) memristors for future ternary data processing, i.e. the direct transitioning of one ternary MLC state to another state. According to the rules of a ternary stored-transfer-adder cell the content of two memristors storing three different resistance values are read out and processed by a sense amplifier to produce a new ternary state for two output memristors. In contrast to own older work the analogue-digital-converting of ternary MLC based memristors with subsequent digital processing is avoided what requires a comparatively high energy budget. The solution is based on an adapted version of an existing sense amplifier circuit realising an in-memory processing for a majority logic developed by our own. We present the new concept and simulation results characterising the functionality for the new memristive ternary MLC for a ReRAM technology from Innovations for High Performance Microelectronics (IHP).