A 6.25 Gb/s Decision Feedback Equalizer used in SerDes for High-speed Backplane Communications

Abstract

A 6.25 Gb/s two-tap DFE (decision feedback equalizer) in high-speed backplane receiver has been designed in a 0.18-mum CMOS. The pipelined architecture in the half-rate DFE achieves an increase in the transmitted data rate over conventional DFE with a small increase in area. Near end data is a 6.25 Gb/s PRBS10 with 0.5 Vp-p, and the DFE recovered data has been measured with jitter (pp) of 3 ps and a horizontal eye-opening of 0.97 UI, a vertical eye opening of 0.48 V.