Architectural design simulation and silicon implementation of a very high fidelity decimation filter for sigma-delta data converters

Abstract

This paper reports on results from the algorithmic design and simulation of a two-path poly-phase decimation filter with 24-bit accuracy over the frequency range from dc to approximately 16 kHz. The filter is suited for very high precision data conversion applications, and has been designed for use with a fourth-order /spl Sigmaspl Delta/ modulator running at 4096 kHz. This paper also reports on the fixed-point architectural design, comparative bit-level simulations and silicon implementation.<>