Stress Migration of Aluminum Backside Interconnect in Xtacking®

Abstract

Backside (BS) interconnects has shown significant advantages in 3D integral circuits for tackling the technology scaling induced frontside (FS) back-end-of-line (BEOL) routing congestion and RC delay challenge. As a representative BS interconnects architecture, Xtacking ® 1.0 & 2.0 innovated by YMTC employs one Al metal layer at backside of memory cell wafer as BS interconnect routing for signal transfer. In this paper, we exploit the effect of silicon substrate to stress migration (SM) reliability of such Al BS interconnects, and offer several process approaches by film stack or film behavior optimization to improve SM performance of Al interconnects with the assistance of numerical simulation. An index of RSM is proposed to reveal the statistic SM performance. Combining experiments and simulation result, a positive relationship is found between hydrostatic stress in numerical simulation and RSM, and it brings a quantitative solution for SM in numerical simulation.