An introduction of QFN-SIP package: Process challenges and technical issues

Abstract

The continuous need for higher levels of integration, lower costs and a growing awareness of complete system configuration is the main driving factor behind the System In Package (SIP) solutions. System In Package today has moved from merely multiple dies into a complete fully functional sub-system that contain a combination of multiple die, passive components, Inductors and IC packages. All these are package into a standard IC package format. QFN-SIP package is introduced as a potential alternative to 2 layer substrate based SIP. Its main advantage being lower cost. Assembly processes for SIP is a combination of what used to be strictly SMT and that of conventional semiconductor processes. These process combinations coupled with layout complexity leads to new process challenges and a consideration at it is applied on the QFN package. This paper discusses in detail the overall process challenges and possible solutions that must be taken into account in order to build a QFN-SIP package that is able to withstand a minimum of MSL3 @ 260?C reflow and the rest of the environmental stress tests as required of an IC package.