Pengyi Cao, Xinpeng Xing, Haigang Feng, Zhihua Wang
{"title":"A Novel Cascode Mixer for NB-IoT Transceiver System in 65nm CMOS","authors":"Pengyi Cao, Xinpeng Xing, Haigang Feng, Zhihua Wang","doi":"10.1109/EDSSC.2018.8487163","DOIUrl":null,"url":null,"abstract":"NB-IoT is a FDD system. Its TX & RX are operated at a fixed frequency offset at the same time. Conventional architecture builds 2 PLLs to support FDD. This paper presents a new architecture which only needs one PLL. Its receiver introduces a novel cascode-mixer structure (Cascaded by two current-mode passive mixers driven by 25% duty-cycle quadrature clocks). The cascode mixer makes two times mixing of RF signals using the LO1 produced by the PLL and the LO2 from the crystal reference. It achieves 18.7dB noise figure and +8.13 dBm IP1dB in simulation with a commercial 65nm RFCMOS process. It consumes 2.8mA from a 1.2V supply. IQ phase mismatch correction is also implemented in this design.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"93 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2018.8487163","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
NB-IoT is a FDD system. Its TX & RX are operated at a fixed frequency offset at the same time. Conventional architecture builds 2 PLLs to support FDD. This paper presents a new architecture which only needs one PLL. Its receiver introduces a novel cascode-mixer structure (Cascaded by two current-mode passive mixers driven by 25% duty-cycle quadrature clocks). The cascode mixer makes two times mixing of RF signals using the LO1 produced by the PLL and the LO2 from the crystal reference. It achieves 18.7dB noise figure and +8.13 dBm IP1dB in simulation with a commercial 65nm RFCMOS process. It consumes 2.8mA from a 1.2V supply. IQ phase mismatch correction is also implemented in this design.