High performance internetworking protocol

Abstract

The use of parallelism for protocol processing in a parallel architecture of an internetworking unit is presented. This architecture consists of pipelines and arrays of processors and supports multiple memory concepts (local and global memory). A high-performance parallel implementation of the internetworking protocol in a gateway is discussed, and selected performance results are presented. The results show that requirements of high-speed networks with throughputs of more than 100 Mb/s can be fulfilled with the proposed parallel architecture and implementation.<>