High-Q inductors and transmission lines on 20 /spl Omega/.cm Si using wafer-level packaging technology

G. Carchon, Xiao Sun, W. De Raedt
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引用次数: 1

Abstract

High Q on-chip inductors and low loss on-chip interconnects and transmission lines are an important roadblock for the further development of Si-based technologies at RF and microwave frequencies. In this paper, inductors are realised on 20 /spl Omega/.cm Si wafers using thin-film Wafer-Level Packaging (WLP) technology: two low K benzo-cyclobutene (BCB, /spl epsiv//sub r/=2.65) dielectric layers and a thick Cu interconnect layer are deposited on floating Si substrates. Inductors with 5/spl mu/m minimum lines and spaces are demonstrated for a 5/spl mu/m thick Cu layer, hereby leading to very compact and high performance inductors: maximum Q-factors of 25 have been obtained for inductances in the range of 1 to 5 nH. It is shown how Q-factor and resonance frequency vary as a function of the inductor layout parameters and the thickness of the BCB and Cu layers. The realised 50 /spl Omega/ CPW lines (lateral dimension of 40 /spl mu/m) have a measured loss of only 0.2 dB/mm@25 GHz. A good agreement between measured and simulated performance has been obtained.
高q电感器和20 /spl ω /传输线。cm Si采用晶圆级封装技术
高Q的片上电感器和低损耗的片上互连和传输线是射频和微波频率下硅基技术进一步发展的重要障碍。在本文中,电感器是在20 /spl ω /上实现的。采用薄膜晶圆级封装(WLP)技术的cm Si晶圆:在浮动Si衬底上沉积两个低K苯并环丁烯(BCB, /spl epsiv//sub r/=2.65)介电层和一个厚Cu互连层。对于5/spl mu/m厚的铜层,最小线和空间为5/spl mu/m的电感器进行了演示,从而实现了非常紧凑和高性能的电感器:在1至5 nH的电感范围内获得了最大q因子25。显示了q因子和谐振频率随电感布局参数和BCB层和Cu层厚度的变化规律。已实现的50 /spl ω / CPW线(横向尺寸为40 /spl mu/m)的测量损耗仅为0.2 dB/mm@25 GHz。实验结果与模拟结果吻合较好。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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