Design and Implementation of Multiple PWM Channels using Universal Asynchronous Receiver Transmitter

Shikhar
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Abstract

Universal Asynchronous Receiver Transmitter (UART) is a communication protocol used for sending and receiving the serial data. It offers short distance communication and it is reliable as well. This paper presents the application of UART module for creating Multiple Pulse Width Modulation (PWM) channels having different duty cycles using serial terminal on Field Programmable Gate Arrays (FPGA). The user can control the duty cycle of the PWM signals through serial terminal. UART module designed for this application features technique for baud rate detection. The design has been synthesized using Verilog Hardware Description Language (HDL) on Lattice Mach XO2 FPGA over a Tiny FPGA A2 module using Lattice Diamond Design software. A Printed Circuit Board (PCB) has been designed to observe the effects of PWM signals with different duty cycles over multiple Light Emitting Diodes (LEDs). The design is verified through simulations and logic analyzer tool. Effects of PWM signals is also observed through the intensity of Multiple LEDs. Maximum frequency that can be obtained on Lattice Mach XO2 FPGA is 133 MHz. The design uses 12.08 MHz frequency for the system clock.
多PWM通道通用异步收发器的设计与实现
通用异步收发器(UART)是一种用于发送和接收串行数据的通信协议。它提供短距离通信,而且很可靠。本文介绍了UART模块在现场可编程门阵列(FPGA)上利用串行终端创建具有不同占空比的多个脉宽调制(PWM)通道的应用。用户可以通过串口控制PWM信号的占空比。为此设计的UART模块具有波特率检测技术。该设计采用Verilog硬件描述语言(HDL)在Lattice Mach XO2 FPGA上,利用Lattice Diamond design软件在一个微型FPGA A2模块上进行了综合。设计了一个印刷电路板(PCB)来观察不同占空比的PWM信号在多个发光二极管(led)上的影响。通过仿真和逻辑分析工具对设计进行了验证。PWM信号的影响也可以通过多个led的强度观察到。在Lattice Mach XO2 FPGA上可以获得的最大频率为133 MHz。本设计采用12.08 MHz频率作为系统时钟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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