Performance Assessment of UTB-SOI MOS Transistor with Negative Capacitance Gate-stack

Abstract

Impact of negative capacitance dielectric material on the device performance of UTB-SOI MOS transistor is investigated with the help of extensive numerical simulation. The negative capacitance characteristics of the dielectric material is modeled by charge dependent ferroelectric polarization effect. With the increase in thickness of ferroelectric material, improvement in sub-threshold characteristics is observed. The sub-threshold swing value goes below Boltzmann limit of 60mV/decade, which is the minimum value of sub-threshold swing for conventional FETs. Internal gate voltage amplification found to be proportional with the thickness of ferroelectric region.