Packet analyzer for JPEG2000 codestreams and its VHDL model

Abstract

In this paper, a packet analyzer for JPEG2000 codestreams is designed and its switching power and cell areas are estimated. This analyzer is intended to treat packets in the PEG2000 codestream, where the packet header and body data are separated from each other for further processing, such as encryption, partial scrambling, data hiding, and error correction. This VHDL-modeled analyzer can work at a bit rate of 50 Mb/s at minimum cost. Thus, it is suitable for real-time applications.