Automated analog filter pair design on the basis of a gyrator-capacitor prototype circuit realised in SI technique

Abstract

The paper presents an algorithmic approach to low sensitive design strategy for switched-current(SI) filter pairs based on a gyrator-capacitor prototype circuit. There is EDA software suite presented its cooperation with associated commercial tools. The functionalities of EDA system are illustrated by the design of filter pair of 5th order that was further realised in TSMC 0.18μm CMOS MS/RF technology. The filter operates at 1.8 V power supply voltage and consumes 2.5 mW. Post layout simulation results are presented and compared with ideal characteristics.