Logic synthesis of 100-percent testable logic networks

Abstract

An approach is presented for the synthesis of 100% testable logic networks based on a test pattern generation system for the identification of redundant faults. A redundancy removal procedure for the elimination of redundant nodes and gates from the network is also presented. Elimination of redundancy is an important task in a logic synthesis system that aims at the synthesis of 100% testable logic networks. Logic synthesis algorithms tend to generate a large number of redundancies, most of which can be easily identified, but some of these redundancies are very hard to identify by logic minimization procedures as well as by conventional test pattern generation algorithms.<>