{"title":"Two methods of design and implementation of ACELP vocoder","authors":"Yi Zhao, Shenmin Zhang, Xiaokang Lin","doi":"10.1109/ICSPCC.2013.6663884","DOIUrl":null,"url":null,"abstract":"ACELP is a type of voice coder algorithm that compresses speech signal based on model parameters of human voice. This paper presents two methods for design and implementation of ACELP vocoder. One is fully hardware design, it is characterized by pipelining and parallel operation of functional units, and it has been tested on an FPGA; the other is hardware-software co-design, it is characterized by dividing the algorithm into hardware part and software part, and it has been tested with NIOS II and FPGA. Experiments' results show that fully hardware implementation can achieve faster speed and smaller latency, and co-design owns shorter design cycle and better voice quality.","PeriodicalId":124509,"journal":{"name":"2013 IEEE International Conference on Signal Processing, Communication and Computing (ICSPCC 2013)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference on Signal Processing, Communication and Computing (ICSPCC 2013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSPCC.2013.6663884","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
ACELP is a type of voice coder algorithm that compresses speech signal based on model parameters of human voice. This paper presents two methods for design and implementation of ACELP vocoder. One is fully hardware design, it is characterized by pipelining and parallel operation of functional units, and it has been tested on an FPGA; the other is hardware-software co-design, it is characterized by dividing the algorithm into hardware part and software part, and it has been tested with NIOS II and FPGA. Experiments' results show that fully hardware implementation can achieve faster speed and smaller latency, and co-design owns shorter design cycle and better voice quality.