ROBUSTLY SCAN-TESTABLE CMOS SEQUENTIAL CIRCUITS

Abstract

In this paper, two methods of applying two-pattern tests for stuck-open faults in scan-testable CMOS sequential circuits are presented. These methods require shifting in only one pattern and require no special latches in the scan chain. Sufficient conditions for 110bust testability of all single FET stuck-open faults and design techniques for robustly scan-testable CMOS sequential circuits are presented. These techniques lead to realizations with at most two additional inputs and some additional FETS in the first-level gates.