Single-Chip 4 Bit 35 GHz Phase-Shifting Receiver with a Gb/s Digital Interface Circuitry

Abstract

Using 0.3 pm gate length GaAs/AIGaAs HEMTs, we have designed and realized a single-chip receiver including one 4 bit 360' phase shifter, two low-noise 35 GHz amplifiers, and one low-power Gb/s digital interface circuit. Desired functions have been measured on-wafer. 16 phase-shifting curves have been obtained with a maximum deviation of 7.5O. The total gain of the millimcteiwavc channel is -7 dB with a phase-dependent deviation of 4.3 dB. The input and the output matching are better than -12 dB. The chip area is 4x2.5 mm'. The dc power consumption is less than 250 mW.