Development and optimization of substrate failure analysis techniques for chip scale packages

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI:10.1109/IPFA.2001.941458

L. B. Yew, C. Francis, S. Mohamed, Tang Wye Mun, L. Ki

引用次数: 1

Abstract

This paper details failure analysis techniques developed to analyze failures of two types of substrate widely used in chip scale packages (CSPs): (a) tape CSP substrate with polyimide (PI) tape, and (b) laminate CSP substrate with bismaleimide-triazine (BT) resin. The structure of both tape and laminate CSP substrates are discussed in detail to aid in understanding the failure analysis techniques of both these materials.

查看原文本刊更多论文

芯片级封装衬底失效分析技术的发展与优化

本文详细介绍了用于分析芯片规模封装(CSP)中广泛使用的两种衬底失效的失效分析技术:(a)聚酰亚胺(PI)带CSP衬底，(b)双马来酰亚胺-三嗪(BT)树脂层压CSP衬底。详细讨论了胶带和层压CSP基板的结构，以帮助理解这两种材料的失效分析技术。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)

自引率

0.00%

发文量