Fractional-N DPLL based low power clocking architecture for 1–14 Gb/s multi-standard transmitter

Abstract

This paper presents a low power clocking solution for multi-standard SerDes applications based on frac-N digital LC PLL for central clock generation and fractional-N ring PLL for local clock generation. The fractional-N LC PLL operates at 7–10 GHz consuming only 8 mW power and occupying 0.15 mm2 of silicon area with integrated jitter of 264 fs. Ring PLL covers from 800 MHz to 4 GHz to support the data rates between 1 to 14 Gb/s. The ring PLL supports dither-less fractional resolution of 250 MHz, corrects I/Q error with split tuning and achieves less than 400 fs integrated jitter. Transmitter works at 14 Gb/s with power efficiency of 0.80 pJ/bit.