Relocatable and resizable SRAM synthesis for via configurable structured ASIC

Abstract

Memory blocks in a structured ASIC are normally pre-customized with fixed sizes and placed at predefined locations. The number of memory blocks is also pre-determined. This imposes a stringent limitation on the use of memory blocks, often creating a situation of either insufficient capacity or considerable waste. To remove this limitation, in this paper we propose a method to create relocatable and resizable SRAM blocks using the same via-configurable logic block to implement both logic gates and 6T SRAM cells. We develop an SRAM compiler to synthesize SRAM blocks of this sort. Our single-port SRAM array uses only 1/3 the area taken by a flip-flop based SRAM array. For dual-port SRAM arrays, this ratio is 2/3. We demonstrate first time the feasibility of deploying a varying number of relocatable and resizable SRAM blocks on a structured ASIC.