SUNNY-RISC: a VLSI RISC micro-architecture

Abstract

A VLSI reduced instruction set computer (RISC) microarchitecture called SUNY-RISC is described. The SUNY-RISC processor is a 16-bit microarchitecture. Most of the instructions are register to register. This approach results in fast execution and simple control logic. SUNY-RISC has some similarities with RISC approaches; however, this machine introduces some new features: support for subroutine call and return and instructions broken into several small steps. The technology used is 1 micron CMOS p-well. SUNY-RISC implements 38 instructions. Some instructions require a double word, for instance load register direct and call. The subsystems described are the arithmetic logic unit and shifter, the internal clock, the constant generator, and special purpose registers.<>