MPEG-2 video decoding on the TMS320C6X DSP architecture

Abstract

This paper explores implementation of MPEG-2 decoding functions (bitstream parsing, IDCT: variable length decoding, motion compensation, dequantization) in software on the TI TMS320C6X architecture. We discuss cycle count estimates for these functions; our estimates are based on optimized, functionally accurate implementations in some cases, and on analysis of C implementations of the function in other cases. We describe how we arrive at these estimates in detail, and discuss how we were able to use automatic compilation effectively for certain functions. We also compare the C6x implementation to other MPEG-2 implementations that have been reported for general purpose CPUs that support a multimedia enhanced instruction set, such as Intel Pentium (MMX), SUN UltraSPARC (VIS), and HP PA (MAX).