Synthesis and physical design of DLX RISC processor

Abstract

A VHDL synthesizable model for AutoLogic II is developed for an unpipelined version of the 32-bit DLX RISC processor, called DLXS. The VHDL RTL model is synthesized, optimized, simulated, and laid out using Mentor Graphics EDA tools. The designed ASIC is based on the CMOSN standard cell library with 0.8 /spl mu/m technology. The processor clock frequency is 33 MHz and the chip area is 8.7/spl times/9.2 mm/sup 2/.