A Novel Static D-Flip-Flop Topology for Low Swing Clocking

Abstract

Low swing clocking is a well known technique to reduce dynamic power consumption of a clock network. A novel static D flip-flop topology is proposed that can reliably operate with a low swing clock signal (down to 50% of the VDD) despite the full swing data and output signals. The proposed topology enables low swing signals within the entire clock network, thereby maximizing the power saved by low swing operation. The proposed flip-flop is compared with existing low swing flip-flops using a 45 nm technology node at a clock frequency of 1.5 GHz. The results demonstrate an average reduction of 38.1% and 44.4% in, respectively, power consumption and power-delay product. The sensitivity of each circuit to clock swing is investigated. The robustness of the proposed topology is also demonstrated by ensuring reliable operation at various process, voltage, and temperature corners.