{"title":"Impacts of hole trapping on the NBTI degradation and recovery in PMOS devices","authors":"H. Lin, D. Lee, S.-C. Ou, C. Chien, T. Huang","doi":"10.1109/IWGI.2003.159188","DOIUrl":null,"url":null,"abstract":"In this paper, impacts of hole trapping on the negative bias temperature instability (NBTI) degradation and recovery in PMOS devices was investigated. Dual-gate p- and n-channel MOSFETs were fabricated using a standard CMOS twin-well technology.","PeriodicalId":221442,"journal":{"name":"Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWGI.2003.159188","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this paper, impacts of hole trapping on the negative bias temperature instability (NBTI) degradation and recovery in PMOS devices was investigated. Dual-gate p- and n-channel MOSFETs were fabricated using a standard CMOS twin-well technology.