Runtime adaptable concurrent error detection for linear digital systems

Abstract

In response to the rising fault susceptibility of ICs due to aggressive device scaling, a number of concurrent error detection (CED) techniques have been proposed. The existing circuit- or logic- level CED techniques aim at the worst case of fault susceptibility. Recognizing that the energy consumption of the circuitry with different CED capability varies significantly, these techniques could result in significant overhead for today's deep sub-micron devices that suffer from strong variation of fault susceptibility. In this paper, we propose a novel RT-level CED technique for linear digital systems. The proposed technique offers run-time adaptable CED so that devices will never overpay the energy bills for their CED needs.