Solder joint fatigue and reliability of chip scale packages: a failure analysis strategy

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI:10.1109/IPFA.2001.941473

S. Mohamed, C. Francis, L. B. Yew, Tang Wye Mun, L. Ki

引用次数: 0

Abstract

This paper outlines an optimal approach for board level chip scale package (CSP) failure analysis, where the chip and printed circuit board (PCB) are analyzed as a single unit. A technique using a combination of cross-section and parallel polishing is described in detail. This technique was specifically developed to inspect key aspects of solder joint fatigue, which are solder joint height, pad dimensions on both package and PCB, substrate warpage, heating profiles/reflow, intermetallic compound (IMC) thickness and solder joint voids.

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芯片规模封装的焊点疲劳与可靠性:失效分析策略

本文概述了电路板级芯片规模封装(CSP)失效分析的最佳方法，其中芯片和印刷电路板(PCB)作为单个单元进行分析。详细介绍了一种采用横截面与平行抛光相结合的技术。该技术专门用于检查焊点疲劳的关键方面，包括焊点高度、封装和PCB上的焊盘尺寸、基板翘曲、加热轮廓/回流、金属间化合物(IMC)厚度和焊点空隙。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)

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