SuperSPARC multichip module

Abstract

An experimental silicon-on-silicon MCM consisting of a SPARC processor, a cache controller and cache memory constructed to study the feasibility of thin film technology for high speed applications is discussed. Results of experiments show that such a design is viable. The trade-offs involved in the selection of a MCM for electrical, thermal and yield performance goals are discussed. Thin film technology provides a viable means of achieving these goals. The lossy nature of the thin film is used to provide series termination and allows high speed pulse propagation to be achieved. Also, the denser design rules permitted by the technology enable a smaller module size.<>