VLSI implementation of ternary gates using Tanner Tool

Abstract

A new era of digital computation investigates the advantages of non-binary machine logic over the conventional binary logic. Multi Valued Logic [MVL] systems, where the radix is greater than 2 are evolving as a thrust area of research. Ternary logic has gained wide popularity and offers several potential opportunities for the improvement of present VLSI circuit designs. Ternary gates form the fundamental element for numerous ternary circuits, making its efficient design and simulation indispensable. This paper presents the implementation and simulation of ternary gates (TNOT, TNAND, TNOR) using injected voltage method. The binary CMOS logic is exploited to achieve the ternary logic values. The performance analysis of the ternary gates in terms of rise time, fall time and power dissipation is examined using Tanner Tool, version 13.02. The prominent subsets (S-Edit, L-Edit, T-Spice and W-Edit) of the tanner tool are used to derive the various device parameters and further verify the functionality of the gates. The layouts of the designed gates are also presented.